Creation and management of timing constraints has become one of the key factors in achieving timing closure of Application Specific Integrated Circuit (ASIC) designs. Efficient and good quality timing constraints significantly affects Turn Around Time (TAT) for design closure.
The complexity of this problem is due several major reasons. The constraints data is often transformed or modified at various stages of the design process, such as at synthesis, physical implementation and Static Timing Analysis (STA) for sign-off, since the requirements for constraints at each of these stages are different. Also, constraint requirements are fundamentally different for the different Electronic Design Automation (EDA) tools in the flow. Tools come from different vendors and perform different functions. One or more characteristics of the constraints, such as the timing values or the syntax of constraint statements, are therefore modified to better fit the particular stage of development or tool being used. This often requires robust checking and verification against an original set of “golden” constraints data at all stages of the design. The designer therefore requires a consistent set of constraints creation guidelines and methods to achieve good quality constraints that can be verified at each stage to ensure that the constraints used at that stage are valid.
Among these, one of the biggest challenges facing the ASIC designers is the configuration of timing constraints for IP cores and integration of these constraints with chip-level constraints when these IP cores are instantiated in an integrated circuit design.
This disclosure provides a generic and automated methodology to create, configure and integrate IP core instance constraints into the chip-level context using industry standard IP representation formats, for example.